1 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 description ? guaranteed ac performance over temperature and voltage: ? >2ghz f max ? < 750ps t pd (matched delay between banks) ? < 15ps within-device skew ? < 200ps rise/fall time ? low jitter design ? < 1ps rms cycle-to-cycle jitter ? < 10ps pp total jitter ? unique input termination and vt pin for dc-coupled and ac-coupled inputs: any differential inputs (lvpecl, lvds, cml, hstl) ? precision differential lvds outputs ? matched delay: all outputs have matched delay, independent of divider setting ? ttl/cmos inputs for select and reset/disable ? two output banks (matched delay) ? bank a: buffered copy of input clock (undivided) ? bank b: divided output (2, 4, 8, 16), two copies ? 2.5v power supply ? wide operating temperature range: ?40c to +85c ? available in 16-pin (3mm x 3mm) mlf ? package features 2.5v, 2ghz any diff. in-to-lvds programmable clock divider/ fanout buffer w/internal termination precision edge ? sy89872u applications ? oc-3 to oc-192 sonet/sdh applications ? transponders ? oscillators ? sonet/sdh line cards rev.: f amendment: /0 issue date: august 2007 this 2.5v low-skew, low-jitter, precision lvds output clock divider accepts any high-speed differential clock input (ac or dc-coupled) cml, lvpecl, hstl or lvds and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. the sy89872u includes two output banks. bank a is an exact copy of the input clock (pass through) with matched propagation delay to bank b, the divided output bank. available divider ratios are 2, 4, 8 and 16. in a typical 622mhz clock system this would provide availability of 311mhz, 155mhz, 77mhz or 38mhz auxiliary clock components. the differential input buffer has a unique internal termination design that allows access to the termination network through a v t pin. this feature allows the device to easily interface to different logic standards. a v ref-ac reference is included for ac-coupled applications. the sy89872u is part of micrel?s high-speed precision edge ? timing and distribution family. for 3.3v applications, consider the sy89873l. for applications that require an lvpecl output, consider the sy89872u. the /reset input asynchronously resets the divider outputs (bank b). in the pass-through function (bank a) the /reset synchronously enables or disables the outputs on the next falling edge of in (rising edge of /in). refer to the ?timing diagram.? functional block diagram typical application precision edge is a registered trademark of micrel, inc. micro leadframe and mlf are registered trademarks of amkor technology, inc. in /in s1 s0 qb 1 /qb 1 qb 0 /qb 0 qa /qa /reset, / disable v t divided by 2, 4, 8 or 16 decoder enable ff enable mux 50 ? 50 ? v ref-ac in /in oc-12 or oc-3 clock generator 622mhz lvpecl clock in /qb qb /qa qa 622mhz/155.5mhz sonet clock generator 622mhz lvds clock out 155.5mhz lvds clock out bank a: 622mhz for oc-12 line card bank b: 155.5mhz for oc-3 line card (set to divide-by-4) precision edge ?
2 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 pin number pin name pin function 1, 2, 3, 4 qb0, /qb0 differential lvds compatible outputs: divide by 2, 4, 8, 16. qb1, /qb1 unused outputs must be terminated with 100y across the pin (q, /q). 5, 6 qa, /qa differential lvds compatible undivided output clock. 7, 14 vcc positive power supply: bypass with 0.1f/0.01f low esr capacitors. 8 /reset, /disable output reset and output enable/disable: internal 25ky pull-up. input threshold is v cc /2. logic low will reset the divider select, and align bank a and bank b edges. in addition, when low, bank a and bank b will be disabled. 12, 9 in, /in differential reference input clock: internal 50y termination resistors to v t input. see ?input interface applications? section. 10 vref-ac re ference voltage: equal to v cc ?1.4v (approx.), and used for ac-coupled applications. maximum sink/source current is 0.5ma. see ?input interface applications? section. 11 vt termination center-tap: for dc-coupled cml and lvds inputs, leave this pin floating. see ?input interface applications? section. 13 gnd ground. 15, 16 s1, s0 select pins: lvttl/cmos logic levels. internal 25ky pull-up resistor. logic high if left unconnected (divided by 16 mode). s0 = lsb. input threshold is v cc /2. pin description /reset /disable s1 s0 bank a output bank b outputs 1 0 0 input clock input clock 2 1 0 1 input clock input clock 4 1 1 0 input clock input clock 8 1 1 1 input clock input clock 16 0 x x qa = low, /qa = high (1) qb0 = low, /qb0 = high (2) qb1 = low, /qb1 = high (2) truth table note 1. on the next negative transition of the input signal. note 2. asynchronous reset/disable function. (see ?timing diagram?) package/ordering information 13 14 15 16 12 11 10 9 1 2 3 4 8 7 6 5 qb0 / qb0 qb1 / qb1 in vt vref-a c /in s0 s1 vc c gn d qa /qa vcc /reset / disable 16-pin mlf ? (mlf-16) ordering information (1) package operating package lead part number type range marking finish sy89872umi mlf-16 industrial 872u sn-pb sy89872umitr (2) mlf-16 industrial 872u sn-pb sy89872umg (3) mlf-16 industrial 872u with nipdau pb-free bar line indicator pb-free sy89872umgtr (2, 3) mlf-16 industrial 872u with nipdau pb-free bar line indicator pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs.
3 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (note 1) supply voltage (v cc ) ................................... ?0.5v to +6.0v input voltage (v in ) .......................................... ?0.5v to v cc lvds output current (i out ) ..................................... 10ma input current in, /in (i in ) .......................................... 50ma v ref-ac input sink/source current (i vref-ac ), note 3 . 2ma lead temperature (soldering, 20sec.) ...................... 260c storage temperature (t s ) ........................ ?65c to +150c operating ratings (note 2) supply voltage range ............................. 2.375v to 2.625v ambient temperature (t a ) ......................... ?40c to +85c package thermal resistance mlf ? ( ja ) still-air ............................................................. 60c/w 500lfpm ........................................................... 54c/w mlf ? ( jb ), note 4 junction-to-board ............................................ 32c/w t a = ?40c to +85c; unless otherwise stated. symbol parameter condition min typ max units v cc power supply voltage 2.375 2.5 2.625 v i cc power supply current no load, max. v cc 75 110 ma r in differential input resistance 90 100 110 y (in-to-/in) v ih input high voltage note 3 0.1 v cc +0.3 v in, /in v il input low voltage note 3 ?0.3 v ih ?0.1 v in, /in v in input voltage swing notes 3, 4 0.1 v cc v v diff_in differential input voltage swing notes 3, 4, 5 0.2 v |i in | input current note 3 45 ma in, /in v ref-ac reference voltage note 6 v cc ?1.525v cc ?1.425 v cc ?1.325 v note 1. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. note 2. specification for packaged product only. note 3. due to the internal termination (see ?input buffer structure? section) the input current depends on the applied voltages at in, /in and v t inputs. do not apply a combination of voltages that causes the input current to exceed the maximum limit! note 4. see ?timing diagram? for v in definition. v in (max.) is specified when v t is floating. note 5. see figures 1c and 1d for v diff definition. note 6. operating using v in is limited to ac-coupled pecl or cml applications only. connect directly to v t pin. dc electrical characteristics (note 1, 2) note 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operati on is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratlng con ditions for extended periods may affect device reliability. note 2. the datasheet limits are not guaranteed if the device is operated beyond the operating ratings. note 3. due to the limited drive capability use for input of the same package only. note 4. junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device?s most negative potential on the pcb .
4 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 v cc = 2.5v 5%; t a = ?40c to +85c; unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 ? v cc v v il input low voltage 0 ? 0.8 v i ih input high current ?125 ? 20 a i il input low current ? ? ?300 a note 1. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. note 2. specification for packaged product only. lvttl/cmos inputs dc electrical characteristics (note 1, 2) v cc = 2.5v 5%; t a = ?40c to +85c; unless otherwise stated. symbol parameter condition min typ max units v out output voltage swing note 5 250 350 450 mv v oh output high voltage note 3 1.475 v v ol output low voltage note 3 0.925 v v ocm output common mode voltage note 4 1.125 1.375 v ? v ocm change in common mode voltage ?50 50 mv note 1. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. note 2. specification for packaged product only. note 3. measured as per figure 1a, 100y across q and /q outputs. note 4. measured as per figure 1b. note 5. see figure 1c. lvds outputs dc electrical characteristics (note 1, 2)
5 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 v cc = 2.5v 5%; t a = ?40c to +85c; unless otherwise stated. symbol parameter condition min typ max units f max maximum toggle frequency output swing: ?200mv 2 ghz maximum input frequency note 3 3.2 ghz t pd differential propagation delay input swing: <400mv 500 625 750 ps in to q input swing: ?400mv 450 575 700 ps t skew within-device skew (differential) note 4 7 15 ps (qb0-to-qb1) within-device skew (differential) note 4 12 30 ps (bank a-to-bank b) part-to-part skew (differential) note 4 250 ps t rr reset recovery time note 5 600 ps t jitter cycle-to-cycle jitter note 6 1 ps rms total jitter note 7 10 ps pp t r , t f rise / fall time (20% to 80%) 70 130 200 ps note 1. measured with 400mv input signal, 50% duty cycle. 100y termination between q and /q, unless otherwise stated. note 2. specification packaged product only. note 3. bank a (pass-through) maximum frequency is limited by the output stage. bank b (input-to-output 2, 4, 8, 16) can accept an input frequency >3ghz, while bank a will be slew rate limited. note 4. skew is measured between outputs under identical transitions. note 5. see ?timing diagram.? note 6. cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. t jitter_cc =t n ?t n+1 , where t is the time between rising edges of the output signal. note 7. total jitter definition: with an ideal clock input, of frequency - f max (device), no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. ac electrical characteristics (note 1, 2)
6 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 timing diagram lvds output v out 100 ? v oh , v ol v oh , v ol gnd figure 1a. lvds differential measurement gnd 50 ? 50 ? v ocm , ? v ocm figure 1b. lvds common mode measurement v in swing / reset in /in /qb qb qa /qa t pd t rr v cc/2 v out swing v in, v ou t 350mv (typica l) figure 1c. single-ended swing 700mv (typical) v diff_in , v diff_ou t figure 1d. differential swing definition of single-ended and differential swing
7 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = 2.5v, v in = 400mv, t a = 25c, unless otherwise stated. 0 50 100 150 200 250 300 350 400 0 500 1000 1500 2000 2500 3000 3500 qa amplitude (mv) frequency (mhz) qa output amplitude vs. frequency 500 550 600 650 700 0 200 400 600 800 1000 1200 1400 propagation delay (ps) input swing (mv) in to q propagation delay vs. input swing 500 525 550 575 600 -40 -20 0 20 40 60 80 100 propagation delay (ps) temperature ( c) in to q propagation delay vs. temperature qa /qa /qb0 qb0 qa @622mhz and qb @155.5mhz (divide-by-4) time (1ns/div.) output swing (100mv/div.) 622mhz output 155.5mhz output 1.25ghz output time (150ps/div.) /q q output swing (50mv/div.) 2ghz output /q q time (100ps/div.) output swing (50mv/div.)
8 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 input buffer structure v cc gnd 50 ? 50 ? in v t / in 1.86k ? 1.86k ? 1.86k ? 1.86k ? figure 2a. simplified differential input buffer v cc gnd s0 s1 /reset r 25k ? r figure 2b. simplified ttl/cmos input buffer
9 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 part number function data sheet link sy89871u 2.5ghz any diff. in-to-lvpecl programmable clock divider/fanout buffer w/internal termination http://www.micrel.com/product-info/products/sy89871u.shtml sy89873l 3.3v, 2ghz any diff. in-to-lvds programmable clock divider/fanout buffer http://www.micrel.com/product-info/products/sy89873l.shtml mlf ? application note http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf hbw solutions new products and applications http://www.micrel.com/product-info/products/solutions.shtml related product and support documentation input interface applications cml in /in v t nc g nd sy89872 u v cc v cc v ref-ac nc figure 3a. dc-coupled cml input interface v cc 0.01 f cml in /in v t g nd sy89872 u v cc v cc v ref-ac figure 3b. ac-coupled cml input interface pecl in /in vt gnd sy89872 u v cc v cc v ref-ac nc * bypass with 0.01? to v cc 50 ? 0 .01? v cc ?v* v cc figure 3c. dc-coupled pecl input interface v cc 0.01 f pecl in /in v t g nd sy89872 u v cc v cc gnd 50 ? 50 ? v ref-ac figure 3d. ac-coupled pecl input interface lvds in /in v t nc g nd sy89872 u v cc v cc v ref-ac nc figure 3e. lvds input interface hstl in /in v t g nd sy89872 u v cc v cc gnd nc v ref-ac figure 3f. hstl input interface
10 precision edge ? sy89872u micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 16-pin micro leadframe ? (mlf-16) package ep- exposed pa d die compside island heat dissipation heavy copper plane heavy copper plane v ee v ee heat dissipation pcb thermal consideration for 16-pin mlf ? package (always solder, or equivalent, the exposed pad to the pcb) package notes: note 1. package meets level 2 moisture sensitivity classification, and is shipped in dry-pack form. note 2. exposed pads must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 944-0970 web http://www.micrel.com the information furnished by micrel in this datasheet is believed to be accurate and reliable. however, no responsibility is as sumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is at purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.
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